In the field of digital electronics, it is quite often that a new design module is added into a pre-existing system which system may be made up of other pre-existing modules. On the other hand, it may occur that some older, pre-existing module must be made to operate in cooperation with a system made up of other new modules. Since there is no clock common to both of the digital systems, they are asynchronous to each other and the problem arises in compatibly transferring digital data between these two systems.
In either of these cases, the new overall system designed must operate compatibly with pre-existing environments and must interface with pre-existing devices that use pre-existing protocols. This type of coexistence of the new circuitry design with the older circuitry design often presents problems in interfacing digital data transfers between such asynchronously clocked modules.
When two different (asynchronous to each other) circuitry systems are joined together for compatible operation, it was generally required that there be a "full synchronization" of signals, that is to say that both ends ("front" inactive-to-active transition and "back" active-to-inactive transition) of the useful signals be synchronized. However, this would introduce a delay of up to a full clock time on each end of the signal, as indicated in FIG. 5 to allow synchronization of digital signals to occur. In some cases, this type of delay of a full clock time at each end of the synchronization signal could be useful and acceptable. However, many times this is not acceptable since it can introduce significant performance degradation.
One situation that needs attention is that of "set-up time". In the herein described circuitry, there is required a time period where an input signal from a first module or system must have its inactive-to-active transition arrive before the transition (rise) of the synchronous clock of a second module or system. This "setup" time is specifically used for a "D" flip-flop such that the input signal to the flip-flop will occur a few moments (set-up time) before the synchronous clock will trigger the flip-flop and charge its "Q" output.
The circuitry of the present disclosure designated as a half-synchronizer circuitry system alleviates the problem of significant performance degradation. The presently described circuitry synchronizes only the back end of the signal while allowing the other front end to propagate through as it is generated from its source module.
The circuitry interface described herein can be used to solve a common but critical problem. Although simple in basic design, the problem solved by "half-synchronizing" a signal is an important and immediate solution.
As previously discussed, since most new designs must operate with other type of modules, they, however, often do not interface well together, that is to say, their timing activity of significant event transitions, being asynchronous to each other, do not necessarily meet each other's optimum timing conditions. Thus the synchronizing of such non-optimum signals is required for a system design program to insure compatibility of data transfer and control signal operations between the different modules or systems.
When required to deter performance degradation and under appropriate conditions, the "half-synchronization" system can provide a safe, reliable and deterministic design without effecting system performance in a negative sense, i.e., by delaying transmission of digital data signals.
The presently described half-synchronizer circuit interface system permits separate (asynchronous) systems to communicate compatibly together with a minimum loss of performance, that is to say, without the additional need for clock time delays which would normally be required.